1. Field of the Invention
The present invention relates to a semiconductor memory cell fabrication method thereof. More particularly, the invention relates to a method for a semiconductor memory cell with non-overlapping active regions in the lengthwise direction with adjacent active regions.
2. Background of the Related Art
FIGS. 1A through 1E are cross-sectional views illustrating sequential fabrication steps of a semiconductor memory cell in the related art.
Referring to FIG. 1A, on a semiconductor substrate 1 having a well (not shown) therein there are sequentially deposited an oxide film 2 and a nitride film 3 so as to define a field region and an active region in a portion of substrate 1, and an active pattern is formed thereon by an etching technique.
As shown in FIG. 1B, using the active pattern as a mask, the semiconductor substrate 1 is oxidized to form a field oxide film 4, and the active pattern is removed by etching to thereby expose an active region 3a externally. A punch-through stop ion-implanting is carried out into the substrate 1. With reference to FIG. 1C, a gate oxide film 5 and a gate polysilicon 6 and at least one gate electrode pattern is sequentially deposited by means of a photolithographic process and an etching process. In FIG. 1C, an N.sup.- field mask is employed to carry out a field stop ion-implanting prior to formation of field oxide film 4. Then, the nitride film 3 is eliminated, a punch-through stop ion-implanting and a channel ion-implanting are carried out, the oxide film 2 is removed, and the gate oxide film 5 and gate polysilicon 6 are sequentially deposited on the exposed active region 3a. Here, a gate electrode pattern can be formed by a photolithographic process and an etching process.
On the substrate 1 including the gate electrode pattern there are respectively deposited a high temperature low pressure dielectric and side wall spacers 7 by a reactive ion etching. Using the gate electrode pattern as a mask, an ion-implanting is carried out into the active region of the substrate 1 to form at least one impurity region 8 which serves as a source/drain region.
As shown in FIG. 1D, an interlayer dielectric (hereinafter, called "ILD") film 9 is formed on the semiconductor substrate 1, including the gate electrode pattern and a contact hole 10 is formed by etching a portion of ILD film 9 to expose therethrough respective portions of more than one impurity region.
Referring to FIG. 1E, a bit line 11 is formed on ILD film 9 including in the contact hole 10 therethrough. Another insulating layer 12 is deposited on ILD film 9 including the bit line 11 and then the insulating layer 12 is etched to expose a portion of the impurity region 8 to thereby form a node contact hole 13. Thereafter, a node electrode 14 is formed on the insulating layer 12 and in the node contact hole 13.
FIGS. 2A through 2C illustrate layouts of partial steps for the above memory cell fabrication process. With reference to FIG. 2A, there are provided a field region defined in accordance with field oxide film 4 grown by a LOCOS method and a plurality of active regions 3a on the field region. The field oxide film 4 grown between the neighboring or adjacent active regions 3a is formed to be thinner ("+" regions) in thickness, compared to other regions. As shown in FIG. 2B, a gate 6 and a field oxide film 4 formed on the active regions 3a. Referring to FIG. 2C, a contact hole 10 and a node contact hole 13 are formed on the active regions 3a.
As described above, when an active region is formed using a LOCOS method during a semiconductor fabrication and if it is applied to a DRAM of more than 64M, the cell area is decreased due to a large scale integration. Therefore, the space between active regions becomes decreased and the thickness of a field oxide film, which grows in a narrow space, becomes excessively thinner relative to the thickness of a field oxide film which is grown so as to isolate devices from a region having larger spaces in between the active regions. As a result, the isolation characteristic can be damaged resulting in a decreased threshold voltage.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.